Name
Abstract | ||
|---|---|---|
Current integration scales allow designing chip multiprocessors (CMP), where cores are interconnected by means of a network-on-chip (NoC). Unfortunately, the small feature size of current integration scales causes some unpredictability in manufactured devices because of process variation. In NoCs, variability may affect links and routers causing them not to match the parameters established at design time. In this paper, we first analyze the way that manufacturing deviations affect the components of a NoC by applying a new comprehensive and detailed within-die variability model to 200 instances of an 8$\,\times\,$8 mesh NoC synthesized using 45 nm technology. Later, we show that GALS-based NoCs present communication bottlenecks under process variation which cannot be avoided by using just device-level solutions but higher level architectural approaches are required. Therefore, to overcome this performance reduction, we draft a novel architectural approach, called performance domains, intended to reduce the negative impact of variability on application execution time. This mechanism is suitable when several applications are simultaneously running in the CMP chip. |
Year | DOI | Venue |
|---|---|---|
2012 | 10.1109/TCAD.2011.2170071 | IEEE Trans. on CAD of Integrated Circuits and Systems |
Keywords | DocType | Volume |
application execution time,Within-Die Process Variation,architectural approach,current integration scale,GALS-Based NoC Performance,process variation,detailed within-die variability model,chip multiprocessors,design time,GALS-based NoCs,novel architectural approach,CMP chip | Journal | 31 |
Issue | ISSN | Citations |
2 | 0278-0070 | 3 |
PageRank | References | Authors |
0.41 | 20 | 5 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Carles HernáNdez | 1 | 176 | 26.56 |
| Antoni Roca | 2 | 140 | 8.51 |
| Federico Silla | 3 | 576 | 56.77 |
| Jose Flich | 4 | 159 | 6.31 |
| Jose Duato | 5 | 893 | 54.65 |