| Efficient Routing in Heterogeneous SoC Designs with Small Implementation Overhead | 1 | 0.35 | 2014 |
| Silicon-aware distributed switch architecture for on-chip networks | 5 | 0.45 | 2013 |
| On the Impact of Within-Die Process Variation in GALS-Based NoC Performance | 3 | 0.41 | 2012 |
| Enabling High-Performance Crossbars through a Floorplan-Aware Design | 6 | 0.53 | 2012 |
| DESA: Distributed Elastic Switch Architecture for efficient networks-on-FPGAS | 6 | 0.48 | 2012 |
| A low-latency modular switch for CMP systems | 7 | 0.48 | 2011 |
| Cost-Efficient On-Chip Routing Implementations for CMP and MPSoC Systems | 27 | 1.05 | 2011 |
| Fault-Tolerant Vertical Link Design for Effective 3D Stacking | 5 | 0.48 | 2011 |
| Characterizing the impact of process variation on 45 nm NoC-based CMPs | 4 | 0.41 | 2011 |
| A Latency-Efficient Router Architecture for CMP Systems | 4 | 0.44 | 2010 |
| VCTlite: Towards an efficient implementation of virtual cut-through switching in on-chip networks. | 0 | 0.34 | 2010 |
| Addressing Manufacturing Challenges with Cost-Efficient Fault Tolerant Routing | 54 | 1.55 | 2010 |
| Improvements on image authentication and recovery using distributed source coding | 3 | 0.43 | 2009 |
| Reduced decoder complexity and latency in pixel-domain Wyner-Ziv video coders | 7 | 0.59 | 2008 |
| Improved pixel-based rate allocation for pixel-domain distributed video coders without feedback channel | 8 | 0.53 | 2007 |
