Name
Abstract | ||
|---|---|---|
There are many challenges inherent in the design of nano-CMOS. This paper describes our recent work relating to the physical design of CMOS circuits. First, in line with variation-aware design, a novel ingenious method of measuring variations in subthreshold characteristics is described. Next, recent RF CMOS issues and approaches to nano-CMOS are discussed. Finally, an on-chip transmission line interconnect developed for global wiring is discussed. |
Year | DOI | Venue |
|---|---|---|
2009 | 10.1587/elex.6.703 | IEICE ELECTRONICS EXPRESS |
Keywords | Field | DocType |
CMOS, scaling, RF CMOS, interconnect integration, integration of diverse functionalities | Transmission line,Computer science,Electronic engineering,CMOS,Subthreshold conduction,Physical design,Electronic circuit,Interconnection,Electrical engineering,Nano cmos | Journal |
Volume | Issue | ISSN |
6 | 11 | 1349-2543 |
Citations | PageRank | References |
1 | 0.37 | 11 |
Authors | ||
5 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Kazuya Masu | 1 | 120 | 36.37 |
| Noboru Ishihara | 2 | 20 | 8.48 |
| Noriaki Nakayama | 3 | 30 | 8.95 |
| Takashi Sato | 4 | 81 | 36.76 |
| Shuhei Amakawa | 5 | 29 | 10.93 |