Title | ||
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Implementing and Evaluating Stream Applications on the Dynamically Reconfigurable Processor |
Abstract | ||
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Dynamically Reconfigurable Processor (DRP) developed by NEC Electronics is a coarse grain reconfigurable processor that selects a data path from the on-chip repository of sixteen circuit configurations, or contexts, to implement different logic on one single DRP chip. Several stream applications have been implemented on DRP-1, the first prototype chip, and evaluation results are presented. By computing parallelly using the Processing Elements(PEs) and distributed memory modules, DRP-1 out-performed Pentium III/4 and embedded CPU MIPS64 in some stream application examples. We also present programming techniques applicable on reconfigurable processors and discuss their feasibility in boosting system performance. |
Year | DOI | Venue |
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2004 | 10.1109/FCCM.2004.42 | FCCM |
Keywords | DocType | ISBN |
drp-1 out-performed pentium iii,prototype chip,stream applications,dynamically reconfigurable processor,reconfigurable processor,stream application,nec electronics,processing elements,coarse grain reconfigurable processor,single drp chip,stream application example,system on a chip,chip,register file,distributed memory,stream processing,application software,embedded computing,state transition,frequency,prototypes,national electric code,fast fourier transforms,computer science | Conference | 0-7695-2230-0 |
Citations | PageRank | References |
15 | 0.97 | 1 |
Authors | ||
13 |
Name | Order | Citations | PageRank |
---|---|---|---|
Noriaki Suzuki | 1 | 41 | 1.83 |
Shunsuke Kurotaki | 2 | 16 | 1.36 |
Masayasu Suzuki | 3 | 106 | 13.17 |
Naoto Kaneko | 4 | 17 | 1.78 |
Yutaka Yamada | 5 | 15 | 0.97 |
Katsuaki Deguchi | 6 | 33 | 3.21 |
Yohei Hasegawa | 7 | 103 | 12.78 |
Hideharu Amano | 8 | 1375 | 210.21 |
Kenichiro Anjo | 9 | 61 | 6.68 |
Masato Motomura | 10 | 91 | 27.81 |
Kazutoshi Wakabayashi | 11 | 219 | 23.60 |
Takeo Toi | 12 | 15 | 0.97 |
Toru Awashima | 13 | 47 | 4.80 |