| Real-Time Tone Mapping: A Survey and Cross-Implementation Hardware Benchmark | 0 | 0.34 | 2022 |
| ProgressiveNN: Achieving Computational Scalability with Dynamic Bit-Precision Adjustment by MSB-first Accumulative Computation. | 0 | 0.34 | 2021 |
| Hidden-Fold Networks: Random Recurrent Residuals Using Sparse Supermasks. | 0 | 0.34 | 2021 |
| STATICA: A 512-Spin 0.25M-Weight Annealing Processor With an All-Spin-Updates-at-Once Architecture for Combinatorial Optimization With Complete Spin–Spin Interactions | 2 | 0.52 | 2021 |
| ExtraFerns: Fully Parallel Ensemble Learning Technique with Non-Greedy yet Minimal Memory Access Training | 0 | 0.34 | 2020 |
| Hardware/Algorithm Co-optimization for Fully-Parallelized Compact Decision Tree Ensembles on FPGAs. | 1 | 0.35 | 2020 |
| A Hardware-efficient Weight Sampling Circuit for Bayesian Neural Networks. | 0 | 0.34 | 2020 |
| ProgressiveNN: Achieving Computational Scalability without Network Alteration by MSB-first Accumulative Computation | 0 | 0.34 | 2020 |
| An Adaptive Global and Local Tone Mapping Algorithm Implemented on FPGA | 0 | 0.34 | 2020 |
| Introduction to the Special Issue on the 2018 International Solid-State Circuits Conference (ISSCC) | 0 | 0.34 | 2019 |
| QUEST: Multi-Purpose Log-Quantized DNN Inference Engine Stacked on 96-MB 3-D SRAM Using Inductive Coupling Technology in 40-nm CMOS | 3 | 0.44 | 2019 |
| A Resource-Efficient Weight Sampling Method for Bayesian Neural Network Accelerators | 0 | 0.34 | 2019 |
| Fpga-Based Annealing Processor With Time-Division Multiplexing | 0 | 0.34 | 2019 |
| Radiography Contrast Enhancement: Smoothed LHE Filter a Practical Solution for Digital X-Rays with Mach Band | 0 | 0.34 | 2019 |
| DeltaNet: Differential Binary Neural Network | 0 | 0.34 | 2019 |
| Dither Nn: Hardware/Algorithm Co-Design For Accurate Quantized Neural Networks | 0 | 0.34 | 2019 |
| Analysis of Smoothed LHE Methods for Processing Images with Optical Illusions | 1 | 0.40 | 2018 |
| Protocomputing Architecture over a Digital Medium Aiming at Real-Time Video Processing. | 0 | 0.34 | 2018 |
| BRein Memory: A Single-Chip Binary/Ternary Reconfigurable in-Memory Deep Neural Network Accelerator Achieving 1.4 TOPS at 0.6 W. | 15 | 0.85 | 2018 |
| Real-time HDTV to 4K and 8K-UHD conversions using anti-aliasing based super resolution algorithm on FPGA. | 1 | 0.40 | 2018 |
| Area and Energy Optimization for Bit-Serial Log-Quantized DNN Accelerator with Shared Accumulators | 0 | 0.34 | 2018 |
| Dither NN: An Accurate Neural Network with Dithering for Low Bit-Precision Hardware | 1 | 0.43 | 2018 |
| New Generation Dynamically Reconfigurable Processor Technology for Accelerating Embedded AI Applications | 0 | 0.34 | 2018 |
| Accelerating deep learning by binarized hardware. | 0 | 0.34 | 2017 |
| An FPGA Realization of a Deep Convolutional Neural Network Using a Threshold Neuron Pruning. | 1 | 0.35 | 2017 |
| In-memory area-efficient signal streaming processor design for binary neural networks | 1 | 0.38 | 2017 |
| A Time-Division Multiplexing Ising Machine on FPGAs. | 0 | 0.34 | 2017 |
| Error Tolerance Analysis of Deep Learning Hardware Using a Restricted Boltzmann Machine Toward Low-Power Memory Implementation | 1 | 0.35 | 2017 |
| Logarithmic Compression for Memory Footprint Reduction in Neural Network Training | 0 | 0.34 | 2017 |
| Motion-vector estimation and cognitive classification on an image sensor/processor 3D stacked system featuring ThruChip interfaces. | 0 | 0.34 | 2016 |
| Motion Vector Estimation Of Textureless Objects Exploiting Reaction-Diffusion Cellular Automata | 1 | 0.48 | 2016 |
| A memory-based realization of a binarized deep convolutional neural network | 4 | 0.42 | 2016 |
| Memory-error tolerance of scalable and highly parallel architecture for restricted Boltzmann machines in Deep Belief Network | 2 | 0.63 | 2016 |
| Image sensor/digital logic 3D stacked module featuring inductive coupling channels for high speed/low-noise image transfer | 3 | 0.52 | 2015 |
| Crosstalk Rejection in 3D-stacked Inter-Chip Communication with Blind Source Separation | 0 | 0.34 | 2015 |
| Enhancing Memcached by Caching Its Data and Functionalities at Network Interface. | 0 | 0.34 | 2015 |
| Introduction to the Special Issue on the 2014 Symposium on VLSI Circuits. | 0 | 0.34 | 2015 |
| Through Chip Interface Based Three-Dimensional Fpga Architecture Exploration | 0 | 0.34 | 2015 |
| Achieving higher performance of memcached by caching at network interface | 0 | 0.34 | 2014 |
| Low-Power Asynchronous Digital Pipeline Based On Mismatch-Tolerant Logic Gates | 0 | 0.34 | 2014 |
| Caching memcached at reconfigurable network interface | 2 | 0.41 | 2014 |
| C-Based adaptive stream processing on dynamically reconfigurable hardware: a case study on window join | 1 | 0.39 | 2013 |
| A restricted dynamically reconfigurable architecture for low power processors | 0 | 0.34 | 2013 |
| Exploiting hardware reconfigurability on window join. | 0 | 0.34 | 2013 |
| C-Based Complex Event Processing on Reconfigurable Hardware | 1 | 0.44 | 2013 |
| 20Gbps C-Based Complex Event Processing | 5 | 0.61 | 2011 |
| Programmable cell array using rewritable solid-electrolyte switch integrated in 90nm CMOS | 10 | 5.43 | 2011 |
| Panel discussions: Impact on society by fusion and harmony of mobile devices, servers, and networks — Their direction of evolutions and optimal roles | 0 | 0.34 | 2011 |
| Implementing and Evaluating Stream Applications on the Dynamically Reconfigurable Processor | 15 | 0.97 | 2004 |
| Efficient metrics and high-level synthesis for dynamically reconfigurable logic | 2 | 0.36 | 2004 |
