Paper Info
Title
Reducing L1 caches power by exploiting software semantics
Abstract
To access a set-associative L1 cache in a high-performance processor, all ways of the selected set are searched and fetched in parallel using physical address bits. Such a cache is oblivious of memory references' software semantics such as stack-heap bifurcation of the memory space, and user-kernel ring levels. This constitutes a waste of energy since e.g., a user-mode instruction fetch will never hit a cache block that contains kernel code. Similarly, a stack access will not hit a cacheline that contains heap data. We propose to exploit software semantics in cache design to avoid unnecessary associative searches, thus reducing dynamic power consumption. Specifically, we utilize virtual memory region properties to optimize the data cache and ring level information to optimize the instruction cache. Our design does not impact performance, and incurs very small hardware cost. Simulations results using SPEC CPU and SPECjapps indicate that the proposed designs help to reduce cache block fetches from DL1 and IL1 by 27% and 57% respectively, resulting in average savings of 15% of DL1 power and more than 30% of IL1 power compared to an aggressively clock-gated baseline.
Year
DOI
Venue
2012
10.1145/2333660.2333750
ISLPED
Keywords
Field
DocType
il1 power,memory reference,cache design,dynamic power consumption,l1 caches power,data cache,software semantics,cache block,dl1 power,l1 cache,instruction cache,simulation,clock gating,virtual memory
Cache invalidation,Cache pollution,Computer science,CPU cache,Cache,Parallel computing,Cache algorithms,Page cache,Real-time computing,Cache coloring,Smart Cache,Operating system
Conference
Citations 
PageRank 
References 
3
0.41
10
Authors
7
Name
Order
Citations
PageRank
Zhen Fang1917.62
Li Zhao260434.84
Xiaowei Jiang371.51
Shih-Lien Lu495867.34
Ravishankar K. Iyer5111975.72
Tong Li630.41
Seung Eun Lee722422.34