Name
Abstract | ||
|---|---|---|
Dynamic logic can provide significant performance and power benefit compared to implementations using static gates. Unfortunately dynamic gates have traditionally suf- fered from low noise margins, which limits their reliability. A new logic family, called complementary dynamic logic (CDL), is presented. CDL replaces the standard keeper logic with a dual dynamic keeper gate that is applicable to all dynamic gate structures. CDL provides dynamic gates with two novel characteristics: hysteresis and arbitrarily configurable noise margins. However, these two benefits come at the cost of reducing the gain and increasing the en- ergy of the dynamic gate. This paper compares the noise, energy, performance, gain, and total transistor width trade- offs of CDL and three other logic families applied to a 65nm cell library consisting of 23 functions. The results show that the performance advantages of dynamic domino gates can be maintained while providing significantly enhanced noise margins using CDL structures. |
Year | DOI | Venue |
|---|---|---|
2007 | 10.1109/VLSISOC.2007.4402495 | VLSI-SOC |
Keywords | Field | DocType |
switches,hysteresis,logic design,dynamic logic | Logic synthesis,Logic gate,Pass transistor logic,Hysteresis,Electronic engineering,Domino,Logic family,Dynamic logic (digital electronics),Engineering,Transistor,Electrical engineering | Conference |
ISBN | Citations | PageRank |
978-1-4244-1710-0 | 0 | 0.34 |
References | Authors | |
9 | 2 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Krishna Santhanam | 1 | 0 | 0.34 |
| Kenneth S. Stevens | 2 | 185 | 25.65 |