Name
Abstract | ||
|---|---|---|
This paper presents a hierarchical modeling technique which, when combined with a test pattern generation algorithm, forms a hierarchical automatic test pattern generation procedure for analog circuits and systems. This hierarchical procedure is demonstrated to be efficient in terms of both memory and computational speed, especially in processing large circuits. Several examples illustrate the hierarchical modeling technique. The test generation algorithm has been validated in several case studies, one of which is described in details. A prototype software tool is available for university and industry use, with possible enhancements to increase the tool applicability in specific design and test environments. |
Year | DOI | Venue |
|---|---|---|
2001 | 10.1109/54.902824 | IEEE Design & Test of Computers |
Keywords | Field | DocType |
hierarchical modeling technique,analog circuits,analog circuit,prototype software tool,hierarchical automatic test pattern,test pattern generation algorithm,hierarchical procedure,hierarchical atpg,tool applicability,test environment,generation procedure,test generation algorithm,observability,automatic test pattern generation,system on a chip,circuit complexity,controllability,system design | Analogue circuits,Automatic test pattern generation,Observability,Analogue electronics,Controllability,Circuit complexity,Computer science,Systems design,Electronic engineering,Computer engineering,Computation | Journal |
Volume | Issue | ISSN |
18 | 1 | 0740-7475 |
Citations | PageRank | References |
17 | 1.67 | 17 |
Authors | ||
5 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Mani Soma | 1 | 497 | 73.41 |
| Sam Huynh | 2 | 28 | 3.33 |
| Jinyan Zhang | 3 | 36 | 4.13 |
| Seongwon Kim | 4 | 105 | 13.05 |
| Giri Devarayanadurg | 5 | 68 | 9.93 |