Paper Info
Title
A hexagonal shaped processor and interconnect topology for tightly-tiled many-core architecture
Abstract
2-Dimensional meshes are the most commonly used Network-on-Chip (NoC) topology for on-chip communication in many-core processor arrays due to their low complexity and excellent match to rectangular processor tiles. However, 2D meshes may incur local traffic congestion for applications with significant levels of traffic with non-neighboring cores, resulting in long latencies and high power consumption. In this paper, we propose an 8-neighbor mesh topology and a 6-neighbor topology with hexagonal-shaped processor tiles. A 16-bit DSP processor and the corresponding processor arrays are implemented in all three topologies. The hexagonal processor tile and arrays of tiles are laid out using industry-standard CAD tools and automatic place and route flow without full-custom design, and result in DRC-clean and LVS-clean layout. A 1080p H.264/AVC residual video encoder and a 54 Mbps 802.11a/11g OFDM wireless LAN baseband receiver are mapped onto all topologies. The 6-neighbor hexagonal grid topology incurs a 2.9% area increase per tile compared to the 4-neighbor 2D mesh, but its much more effective inter-processor interconnect yields an average total application area reduction of 21%, an average power reduction of 17%, and a total application inter-processor communication distance reduction of 19%.
Year
DOI
Venue
2012
10.1109/VLSI-SoC.2012.6379022
VLSI-SOC
Keywords
Field
DocType
integrated circuit interconnections,tightly-tiled many-core architecture,route flow,hexagonal shaped processor tiles,microprocessor chips,8-neighbor mesh topology,h.264/avc residual video encoder and,word length 16 bit,network topology,on-chip communication,lvs-clean layout,many-core processor arrays,automatic place,total application area reduction,cad tools,total application interprocessor communication distance reduction,circuit cad,dsp processor,interconnect topology,interprocessor interconnect,local traffic congestion,6-neighbor topology,2d meshes,integrated circuit layout,802.11a/11g ofdm wireless lan baseband receiver,power reduction,network-on-chip,video codecs,drc-clean layout,routing,network on chip,topology
Integrated circuit layout,Mesh networking,Baseband,Hexagonal tiling,Network on a chip,Place and route,Network topology,Encoder,Engineering,Computer hardware,Embedded system
Conference
ISSN
ISBN
Citations 
2324-8432
978-1-4673-2656-8
2
PageRank 
References 
Authors
0.39
9
2
Name
Order
Citations
PageRank
Zhibin Xiao1224.85
Bevan M. Baas229527.78