Name
Abstract | ||
|---|---|---|
This paper presents a new dynamic latched comparator which shows lower input-referred latch offset voltage and higher load drivability than the conventional dynamic latched comparators. With two additional inverters inserted between the input- and output-stage of the conventional double-tail dynamic comparator, the gain preceding the regenerative latch stage was improved and the complementary version of the output-latch stage, which has bigger output drive current capability at the same area, was implemented. As a result, the circuit shows up to 25% less input-referred latch offset voltage and 44% less sensitivity of the delay versus the input voltage difference (delay/log(ΔVin)), which is about 17.2ps/decade, than the conventional double-tail latched comparator at approximately the same area and power consumption. |
Year | DOI | Venue |
|---|---|---|
2010 | 10.1145/1785481.1785493 | ACM Great Lakes Symposium on VLSI |
Keywords | Field | DocType |
conventional double-tail dynamic comparator,conventional dynamic latched comparators,input voltage difference,new dynamic latched comparator,conventional double-tail latched comparator,current capability,bigger output drive,additional inverters,output-latch stage,dual-rail dynamic latched comparator,complementary version | Comparator,Input offset voltage,Computer science,Voltage,Low offset,Real-time computing,Electronic engineering,Comparator applications,Power consumption | Conference |
Citations | PageRank | References |
0 | 0.34 | 5 |
Authors | ||
2 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Heungjun Jeon | 1 | 26 | 3.63 |
| Yong-bin Kim | 2 | 338 | 55.72 |