Name
Title | ||
|---|---|---|
A 32 Gb/s Data-Interpolator Receiver With Two-Tap DFE Fabricated With 28-nm CMOS Process. |
Abstract | ||
|---|---|---|
A 32-Gb/s data-interpolator receiver for electrical chip-to-chip communications is introduced. The receiver front-end samples incoming data by using a blind clock signal, which has a plesiochronous frequency-phase relation with the data. Phase alignment between the data and decision timing is achieved by interpolating the input-signal samples in the analog domain. The receiver has a continuous-tim... |
Year | DOI | Venue |
|---|---|---|
2013 | 10.1109/JSSC.2013.2278805 | IEEE Journal of Solid-State Circuits |
Keywords | Field | DocType |
Clocks,Receivers,Interpolation,Capacitors,Timing,Switches,Decision feedback equalizers | Clock signal,Plesiochronous system,Phase alignment,Comparator,Radio receiver design,Computer science,Interpolation,Cmos process,CMOS,Electronic engineering | Journal |
Volume | Issue | ISSN |
48 | 12 | 0018-9200 |
Citations | PageRank | References |
2 | 0.54 | 12 |
Authors | ||
11 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Yoshiyasu Doi | 1 | 115 | 17.56 |
| Takayuki Shibasaki | 2 | 66 | 12.00 |
| Takumi Danjo | 3 | 12 | 2.35 |
| Win Chaivipas | 4 | 87 | 9.07 |
| Takushi Hashida | 5 | 38 | 6.03 |
| Hiroki Miyaoka | 6 | 13 | 2.68 |
| Masanori Hoshino | 7 | 2 | 0.87 |
| Yoichi Koyanagi | 8 | 68 | 13.60 |
| Takuji Yamamoto | 9 | 100 | 22.09 |
| Sanroku Tsukamoto | 10 | 109 | 18.09 |
| H. Tamura | 11 | 29 | 5.21 |