Name
Papers
Collaborators
TAKAYUKI SHIBASAKI
21
79
Citations 
PageRank 
Referers 
66
12.00
276
Referees 
References 
303
69
Search Limit
100303
Title
Citations
PageRank
Year
Digital Annealer for High-Speed Solving of Combinatorial optimization Problems and Its Applications.00.342020
6.8 A 36Gb/s Adaptive Baud-Rate CDR with CTLE and 1-Tap DFE in 28nm CMOS10.382019
A 30Gb/s 2x Half-Baud-Rate CDR00.342019
F5: Advanced optical communication: From devices, circuits, and architectures to algorithms.00.342018
6.6 A 22.5-to-32Gb/s 3.2pJ/b referenceless baud-rate digital CDR with DFE and CTLE in 28nm CMOS30.492017
Session 6 overview: Ultra-high-speed wireline00.342017
A 22.5-to-32-Gb/s 3.2-pJ/b Referenceless Baud-Rate Digital CDR With DFE and CTLE in 28-nm CMOS.20.402017
24 to 34-Gb/s ×4 multi-rate VCSEL-based optical transceiver with referenceless CDR00.342016
3.5 A 56Gb/s NRZ-electrical 247mW/lane serial-link transceiver in 28nm CMOS101.142016
A 28.3 Gb/s 7.3 pJ/bit 35 dB backplane transceiver with eye sampling phase adaptation in 28 nm CMOS.00.342016
22.8 A 24-to-35Gb/s x4 VCSEL driver IC with multi-rate referenceless CDR in 0.13um SiGe BiCMOS00.342015
22.7 4×25.78Gb/s retimer ICs for optical links in 0.13μm SiGe BiCMOS00.342015
25.78-Gb/s VCSEL-based optical transceiver with retimer-embedded driver and receiver ICs00.342015
A 56-Gb/s receiver front-end with a CTLE and 1-tap DFE in 20-nm CMOS60.742014
A 32 Gb/s Data-Interpolator Receiver With Two-Tap DFE Fabricated With 28-nm CMOS Process.20.542013
A 60-Ghz Injection-Locked Frequency Divider Using Multi-Order Lc Oscillator Topology For Wide Locking Range00.342011
A 3 Watt 39.8–44.6 Gb/s Dual-Mode SFI5.2 SerDes Chip Set in 65 nm CMOS110.852010
A Single-40 Gb/s Dual-20 Gb/s Serializer IC With SFI-5.2 Interface in 65 nm CMOS142.232009
A single-40Gb/s dual-20Gb/s serializer IC with SFI-5.2 interface in 65nm CMOS50.572009
20-GHz Quadrature Injection-Locked LC Dividers With Enhanced Locking Range100.842008
18-Ghz Clock Distribution Using A Coupled Vco Array20.442007