Name
Abstract | ||
|---|---|---|
In this paper we propose a method for synthesizing sequentialcircuits to reduce the number of gates and flip-flops by removingboth combinationally and sequentially redundant faults. In order toremove sequentially redundant faults these faults are converted intocombinationally redundant faults by using retiming techniques and thecombinationally redundant faults can be removed by using a testpattern generation method for combinational circuits. To simplify agiven circuit retiming is utilized for two purposes in thismethod. One is to find sequentially redundant faults and another is toreduce the number of flip-flops and gates. Before and after eachretiming the combinationally redundant faults are removed.Experimental results for ISCAS ‘89 benchmark circuits show that thismethod can remove many of sequentially redundant faults and canreduce a large number of gates and flip-flops. |
Year | DOI | Venue |
|---|---|---|
1997 | 10.1023/A:1008251901959 | J. Electronic Testing |
Keywords | Field | DocType |
synthesis of sequential circuits,redundant fault,retiming,redundancy removal,sequentially redundant fault | Retiming,Sequential logic,Pattern generation,Computer science,Parallel computing,Electronic engineering,Real-time computing,Combinational logic,Redundancy (engineering),Electronic circuit,AND gate | Journal |
Volume | Issue | ISSN |
11 | 1 | 1573-0727 |
Citations | PageRank | References |
2 | 0.54 | 20 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Hiroyuki Yotsuyanagi | 1 | 70 | 19.04 |
| Seiji Kajihara | 2 | 989 | 73.60 |
| Kozo Kinoshita | 3 | 756 | 118.08 |