Name
Abstract | ||
|---|---|---|
Previous procedures for synthesis of testable logic guarantee that all faults in the synthesized circuits are detectable. However, the detectability of many faults in these circuits can be very low leading to poor random pattern testability. A new procedure to perform logic synthesis that synthesizes random pattern testable multilevel circuits is proposed. Experimental results show that the circuits synthesized by the proposed procedure tstfx are significantly more random pattern testable and smaller than those synthesized using its counterpart fast_extract (fx) in SIS. The proposed synthesis procedure design circuits that require only simple random pattern generators in built-in self-test, thereby obviating the need for complex BIST circuitry. |
Year | DOI | Venue |
|---|---|---|
1994 | 10.1109/ICCAD.1994.629754 | ICCAD |
Keywords | Field | DocType |
previous procedure,proposed synthesis procedure design,random pattern testable logic,simple random pattern generator,new procedure,synthesized circuit,random pattern testable,logic synthesis,poor random pattern testability,testable logic guarantee,proposed procedure tstfx,logic circuits,fault detection | Stuck-at fault,Logic synthesis,Logic gate,Logic optimization,Computer science,Algorithm,Real-time computing,Electronic engineering,Resistor–transistor logic,Register-transfer level,Logic family,Asynchronous circuit | Conference |
ISSN | ISBN | Citations |
1063-6757 | 0-89791-690-5 | 16 |
PageRank | References | Authors |
1.77 | 13 | 2 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Chen-Huan Chiang | 1 | 53 | 7.33 |
| Sandeep K. Gupta | 2 | 1980 | 229.01 |