Name
Abstract | ||
|---|---|---|
Ultra-low voltage is now a well-known solution for energy constrained applications designed using nanometric process technologies. This work is focused on setting up an automated methodology to enable the design of ultra-low voltage digital circuits exclusively using standard EDA tools. To achieve this goal, a 0.35V energy-delay optimized library was developed. This library, fully compliant with standard library design flow and characterization, was verified through the design and fabrication of a BCH decoder circuit, following a standard front-end to back-end flow. At 0.33V, it performs at 600 kHz with a dynamic energy consumption reduced by a factor 14x from nominal 1.1V. Based on this design, experiments, and preliminary silicon results, two additional libraries were developed in order to enhance future ultra-low voltage circuit performance. |
Year | DOI | Venue |
|---|---|---|
2011 | 10.1145/1970353.1970369 | ACM Trans. Design Autom. Electr. Syst. |
Keywords | Field | DocType |
additional library,bch decoder circuit,standard front-end,standard eda tool,future ultra-low voltage circuit,ultra-low voltage digital circuit,standard cell libraries,back-end flow,energy-delay optimized library,ultra-low voltage,standard library design flow,ultra-low power applications,circuit,logic,design,circuit design,cmos,digital circuits,library,energy,subthreshold,methodology,front end | Digital electronics,Computer science,Voltage,Real-time computing,BCH code,Electronic engineering,Design flow,CMOS,Electronic design automation,Standard cell,Subthreshold conduction | Journal |
Volume | Issue | ISSN |
16 | 3 | 1084-4309 |
Citations | PageRank | References |
6 | 0.81 | 12 |
Authors | ||
6 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Fady Abouzeid | 1 | 32 | 6.98 |
| Sylvain Clerc | 2 | 36 | 8.56 |
| Fabian Firmin | 3 | 6 | 0.81 |
| Marc Renaudin | 4 | 498 | 49.15 |
| Tiempo Sas | 5 | 6 | 0.81 |
| Gilles Sicard | 6 | 6 | 0.81 |