| FIRECAP: Fail-Reason Capturing hardware module for a RISC-V based System on a Chip | 0 | 0.34 | 2021 |
| A 140 nW, 32.768 kHz, 1.9 ppm/°C Leakage-Based Digitally Relocked Clock Reference with 0.1 ppm Long-Term Stability in 28nm FD-SOI | 0 | 0.34 | 2018 |
| A 2.7 pJ/cycle 16 MHz, 0.7 $\mu\text{W}$ Deep Sleep Power ARM Cortex-M0+ Core SoC in 28 nm FD-SOI | 1 | 0.40 | 2018 |
| A 0.40pJ/cycle 981 μm<sup>2</sup> voltage scalable digital frequency generator for SoC clocking | 0 | 0.34 | 2017 |
| A 2.7pJ/cycle 16MHz SoC with 4.3nW power-off ARM Cortex-M0+ core in 28nm FD-SOI. | 0 | 0.34 | 2017 |
| 30% static power improvement on ARM Cortex®-A53 using static biasing-anticipation. | 0 | 0.34 | 2016 |
| 8.4 A 0.33V/-40°C process/temperature closed-loop compensation SoC embedding all-digital clock multiplier and DC-DC converter exploiting FDSOI 28nm back-gate biasing | 17 | 1.30 | 2015 |
| Frequency and voltage effects on SER on a 65nm Sparc-V8 microprocessor under radiation test | 0 | 0.34 | 2015 |
| Design and performance parameters of an ultra-low voltage, single supply 32bit processor implemented in 28nm FDSOI technology | 0 | 0.34 | 2015 |
| 28nm FD-SOI technology and design platform for sub-10pJ/cycle and SER-immune 32bits processors. | 2 | 0.40 | 2015 |
| 27.1 A 460MHz at 397mV, 2.6GHz at 1.3V, 32b VLIW DSP, embedding F MAX tracking | 0 | 0.34 | 2014 |
| 28nm CMOS, energy efficient and variability tolerant, 350mV-to-1.0V, 10MHz/700MHz, 252bits frame error-decoder. | 4 | 0.57 | 2012 |
| A 0.32V, 55fJ per bit access energy, CMOS 65nm bit-interleaved SRAM with radiation Soft Error tolerance | 1 | 0.40 | 2012 |
| A 240mV 1MHz, 340mV 10MHz, 40nm CMOS, 252 bits frame decoder using ultra-low voltage circuit design platform. | 1 | 0.39 | 2011 |
| 40nm CMOS 0.35V-Optimized Standard Cell Libraries for Ultra-Low Power Applications | 6 | 0.81 | 2011 |
