Name
Abstract | ||
|---|---|---|
A design approach is proposed to automatically identify and exploit runtime reconfiguration opportunities with optimised resource utilisation by eliminating idle functions. We introduce Reconfiguration Data Flow Graph, a hierarchical graph structure enabling reconfigurable designs to be synthesised in three steps: function analysis, configuration organisation, and runtime solution generation. The synthesised reconfigurable designs are dynamically evaluated and selected under various runtime conditions. Three applications—barrier option pricing, particle filter, and reverse time migration—are used in evaluating the proposed approach. The runtime solutions approximate their theoretical performance by eliminating idle functions and are 1.31 to 2.19 times faster than optimised static designs. FPGA designs developed with the proposed approach are up to 43.8 times faster than optimised CPU reference designs and 1.55 times faster than optimised GPU designs. |
Year | DOI | Venue |
|---|---|---|
2013 | 10.1109/FCCM.2013.58 | ACM Transactions on Reconfigurable Technology and Systems |
Keywords | Field | DocType |
hierarchical graph structure,particle filtering (numerical methods),reconfiguration data flow graph,reverse time migration,automating elimination,optimised cpu reference design,run-time reconfiguration opportunities,configuration organisation,idle functions elimination automation,fpga designs,particle filter,optimised static design,reconfigurable designs,cpu reference optimisation,optimised gpu design,high performance computing,idle functions,function analysis,run-time solution,integrated circuit design,static designs optimisation,barrier option pricing,gpu designs optimisation,design approach,field programmable gate arrays,run-time reconfiguration opportunity,reconfigurable computing,resource utilisation,pricing,run-time solution generation,run-time reconfiguration,parallel processing,hardware,resource management,algorithm design and analysis,memory management | Supercomputer,Idle,Computer science,Particle filter,Parallel computing,Field-programmable gate array,Data-flow analysis,Real-time computing,Integrated circuit design,Control reconfiguration,Embedded system,Reconfigurable computing | Conference |
Volume | Issue | ISBN |
8 | 3 | 978-1-4673-6005-0 |
Citations | PageRank | References |
9 | 0.79 | 21 |
Authors | ||
5 | ||