Name
Abstract | ||
|---|---|---|
This paper describes a novel modeling method for Gate Delay Faults. The methodology considers each Gate Delay Fault as equivalent to a set of Transition Delay Faults in the propagation paths of the affected port. The main advantage of using this model is that it does not need any explicit timing information and it allows to predict the effect of gate delay faults by using classical Transition Delay fault simulators. In this work, we exploit the modeling method to classify the circuit behavior depending on the delay range, the proposed algorithm finally works out the delay size ranges introducing no effect, small delay and gross delay fault effect. Results are carried out on the full scan version of ISCAS85, ISCAS89 and ITC99 benchmarks. |
Year | DOI | Venue |
|---|---|---|
2011 | 10.1109/DFT.2011.53 | Defect and Fault Tolerance in VLSI and Nanotechnology Systems |
Keywords | Field | DocType |
small delay,gate delay fault,delay range,novel modeling method,modeling method,classical transition delay fault,delay size,transition delay faults,gate delay faults,gross delay fault effect,logic gates,benchmark testing,fault model | Delay calculation,Stuck-at fault,Logic gate,Fault modeling,Computer science,Real-time computing,Exploit,Electronic engineering,Elmore delay,Benchmark (computing),Fault indicator | Conference |
ISSN | ISBN | Citations |
1550-5774 | 978-1-4577-1713-0 | 1 |
PageRank | References | Authors |
0.37 | 5 | 5 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| P. Bernardi | 1 | 144 | 16.93 |
| M. Sonza Reorda | 2 | 1099 | 114.76 |
| A. Bosio | 3 | 113 | 15.51 |
| P. Girard | 4 | 478 | 41.91 |
| S. Pravossoudovitch | 5 | 689 | 54.12 |