Paper Info
Title
Reservation-based Network-on-Chip Timing Models for Large-scale Architectural Simulation
Abstract
Architectural simulation is an essential tool when it comes to evaluating the design of future many-core chips. However, reproducing all the components of such complex systems precisely would require unreasonable amounts of computing power. Hence, a trade off between accuracy and compute time is needed. For this reason most state-of-the-art tools do not have accurate models for the networks-on-chip, and rely on timing models that permit fast-simulation. Generally, these models are very simplistic and disregard contention for the use of network resources. As the number of nodes in the network-on-chip grows, fluctuations with contention and other parameters can considerably affect the accuracy of such models. In this paper we present and evaluate a collection of timing models based on a reservation scheme which consider the contention for the use of network resources. These models provide results quickly while being more accurate than simple no-contention approaches.
Year
DOI
Venue
2012
10.1109/NOCS.2012.18
NOCS
Keywords
Field
DocType
permit fast-simulation,accurate model,large-scale architectural simulation,reservation-based network-on-chip timing models,reservation scheme,complex system,essential tool,architectural simulation,timing model,network resource,future many-core chip,disregard contention,benchmark testing,computer architecture,accuracy,complex systems,network resources,simulation,computational modeling,network on chip
Complex system,Reservation,Resource (disambiguation),Load modeling,Computer science,Parallel computing,Network on a chip,Real-time computing,Benchmark (computing)
Conference
Citations 
PageRank 
References 
2
0.37
29
Authors
5
Name
Order
Citations
PageRank
Javier Navaridas120123.58
Behram Khan2314.03
Salman Khan338741.05
Paolo Faraboschi497481.37
Mikel Luján554046.40