Name
Abstract | ||
|---|---|---|
As circuits continue to scale to smaller feature sizes, wearout and latent defects are expected to cause an increasing number of errors in the field. Online error detection techniques, including logic implication-based checker hardware, are capable of detecting at least some of these errors as they occur. However, recovery may be expensive, and the underlying problem may lead to multiple failures of a core over time. In this article, we will investigate the diagnostic capability of logic implications to identify possible failure locations when an error is detected online. We will then utilize this information to select a highly efficient test set that can be used to effectively test the identified suspect locations in both the failing core and in other identical cores in the system. |
Year | DOI | Venue |
|---|---|---|
2012 | 10.1145/2390191.2390205 | ACM Trans. Design Autom. Electr. Syst. |
Keywords | Field | DocType |
suspect fault identification,multiple failure,efficient test set,checker hardware,latent defect,increasing number,logic implication,identical core,possible failure location,online error detection technique,diagnostic capability,invariance | Invariant (physics),Computer science,Error detection and correction,Real-time computing,Suspect,Electronic circuit,Test set | Journal |
Volume | Issue | ISSN |
18 | 1 | 1084-4309 |
Citations | PageRank | References |
4 | 0.39 | 40 |
Authors | ||
6 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Jennifer Dworak | 1 | 4 | 0.39 |
| Kundan Nepal | 2 | 41 | 5.88 |
| Nuno Alves | 3 | 41 | 3.74 |
| Yiwen Shi | 4 | 23 | 2.44 |
| Nicholas Imbriglia | 5 | 4 | 0.39 |
| R. Iris Bahar | 6 | 878 | 84.31 |