Name
Abstract | ||
|---|---|---|
Balancing cache energy efficiency and reliability is a major challenge for future multicore system design. Supply voltage reduction is an effective tool to minimize cache energy consumption, usually at the expense of increased number of errors. To achieve substantial energy reduction without degrading reliability, we propose an adaptive fault-tolerant cache architecture, which provides appropriate error control for each cache line based on the number of faulty cells detected at reduced supply voltages. Our experiments show that the proposed approach can improve energy efficiency by more than 25% and energy-execution time product by over 10%, while improving reliability up to 4X using Mean-Error-To-Failure (METF) metric, compared to the next-best solution at the cost of 0.08% storage overhead. |
Year | DOI | Venue |
|---|---|---|
2013 | 10.7873/DATE.2013.157 | DATE |
Keywords | Field | DocType |
fault tolerance,cache,error correction,energy efficiency,multicore,computer architecture,vlsi | Cache pollution,Computer science,Efficient energy use,CPU cache,Cache,Parallel computing,Cache-only memory architecture,Cache algorithms,Real-time computing,Smart Cache,Energy consumption | Conference |
ISSN | Citations | PageRank |
1530-1591 | 5 | 0.41 |
References | Authors | |
11 | 3 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Paul Ampadu | 1 | 285 | 28.55 |
| Meilin Zhang | 2 | 40 | 3.16 |
| Vladimir Stojanovic | 3 | 1410 | 155.48 |