Name
Abstract | ||
|---|---|---|
Fault injection in circuit level has proved to be cumbersome and time-consuming when employed to characterize the soft error sensitivity of digital circuits, hence new generation of CAD tool is required to automate the faults insertion and the validation ... |
Year | DOI | Venue |
|---|---|---|
2008 | 10.1109/PRDC.2008.8 | PRDC |
Keywords | Field | DocType |
circuit level,two-rail logic circuits,soft error sensitivity,fault injection,digital circuit,cad tool,new generation,faults insertion,path delay fault test,testability,normal operator,monotone function,logic circuits | Testability,Monotonic function,Logic gate,Pass transistor logic,Logic optimization,Computer science,Path delay,Real-time computing,Electronic engineering,Strongly fault secure,Test set | Conference |
Citations | PageRank | References |
1 | 0.39 | 4 |
Authors | ||
2 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Kazuteru Namba | 1 | 114 | 27.93 |
| Hideo Ito | 2 | 100 | 17.45 |