Title
XTREM: a power simulator for the Intel XScale® core
Abstract
Managing power concerns in icroprocessors has become a pressing research problem across the domains of computer architecture, CAD, and compilers. As a result, several parameterized cycle-level power simulators have been introduced. While these simulators can be quite useful for microarchitectural studies, their generality limits how accurate they can be for any one chip family. Furthermore, their hardware focus means that they do not explicitly enable studying the interaction of different software layers, such as Java applications and their underlying Runtime system software.This paper describes and evaluates XTREM, a power simulation tool tailored for the Intel XScale icroarchitecture. In building XTREM, our goals were to develop a icroarchitecture simulator that, while still offering size parameterizations for cache, TLB, etc., more accurately reflected a realistic processor pipeline. We present a detailed set of validations based on ultimeter power measurements and hardware performance counter sampling. Based on these validations across a wide range of stressmarks, Java benchmarks, and non-Java benchmarks, XTREM has an average performance error of only 6.5% and an even smaller average power error: 4%. The paper goes on to present a selection of application studies enabled by the simulator. For example, presenting power behavior vs. time for selected embedded C and Java CLDC benchmarks, we can make power distinctions between the two programming domains as well as distinguishing Java application (JITted code) power from Java Runtime system power. We also study how the Intel XScale core 's power consumption varies for different data activity factors, creating power swings as large as 50mW for a 200Mhz core. We are planning to release XTREM for wider use, and feel that it offers a useful step forward for compiler and embedded software designers.
Year
DOI
Venue
2004
10.1145/997163.997180
Proceedings of the 2007 ACM SIGPLAN/SIGBED conference on Languages, compilers, and tools for embedded systems
Keywords
Field
DocType
java,computer architecture,chip,embedded software
Hardware performance counter,Programming language,Computer science,Runtime system,Microarchitecture,Computer architecture,Embedded software,Simulation,Microprocessor,Parallel computing,Compiler,Java,Translation lookaside buffer,Embedded system
Conference
Volume
Issue
ISSN
39
7
0362-1340
ISBN
Citations 
PageRank 
1-58113-806-7
50
7.40
References 
Authors
7
5
Name
Order
Citations
PageRank
Gilberto Contreras141036.87
Margaret Martonosi28647715.76
Jinzhan Peng3638.94
Roy Ju412813.58
Guei-Yuan Lueh540137.41