Name
Playground
About
FAQ
GitHub
Playground
Shortest Path Finder
Community Detector
Connected Papers
Author Trending
b huai
Lukas Pezawas
Claudia Calabrese
Maria Concetta Palumbo
N. V. Nguyen
Jhonathan Pinzon
Giovanni Venturelli
Chen Ma
Radu Timofte
Kuanrui Yin
Home
/
Author
/
GUEI-YUAN LUEH
Author Info
Open Visualization
Name
Affiliation
Papers
GUEI-YUAN LUEH
Intel Corp., Santa Clara, California
23
Collaborators
Citations
PageRank
57
401
37.41
Referers
Referees
References
950
453
195
Search Limit
100
950
Publications (23 rows)
Collaborators (57 rows)
Referers (100 rows)
Referees (100 rows)
Title
Citations
PageRank
Year
C-for-metal: high performance SIMD programming on intel GPUs
1
0.41
2021
A Lock-Free Skiplist for Integrated Graphics Processing Units
0
0.34
2019
IGC: the open source Intel graphics compiler
2
0.40
2019
SIMD-node Transformations for Non-blocking Data Structures.
0
0.34
2019
Register allocation for Intel processor graphics.
2
0.37
2018
Bothnia: a dual-personality extension to the Intel integrated graphics driver
0
0.34
2011
The XTREM power and performance simulator for the Intel XScale core: Design and experiences
18
0.69
2007
EXOCHI: architecture and programming environment for a heterogeneous multi-core multithreaded system
88
8.41
2007
Data and computation transformations for Brook streaming applications on multiprocessors
55
3.65
2006
A comprehensive study of hardware/software approaches to improve TLB performance for java applications on embedded systems
3
0.41
2006
Parallel Processing Of A Raytracer For Gpu Vs. For Cpu
1
0.52
2005
A Code Generation Algorithm for Affine Partitioning Framework
1
0.36
2005
XAMM: a high-performance automatic memory management system with memory-constrained designs
1
0.37
2005
XTREM: a power simulator for the Intel XScale® core
50
7.40
2004
Inter-procedural stacked register allocation for itanium® like architecture
2
0.39
2003
Practicing JUDO: Java under dynamic optimizations
93
5.03
2000
Fusion-based register allocation
26
1.35
2000
Support for garbage collection at every instruction in a Java compiler
26
2.97
1999
Call-cost directed register allocation
9
0.73
1997
Code reuse in an optimizing compiler
9
0.99
1996
Global Register Allocation Based on Graph Fusion
13
1.24
1996
Modeling Instruction-Level Parallelism for Software Pipelining
1
0.37
1993
Modeling Instruction-Level Parallelism for Software Pipelining
0
0.34
1993
1