Paper Info
Title
A high-performance low VMIN 55nm 512Kb disturb-free 8T SRAM with adaptive VVSS control.
Abstract
This paper describes a high-performance low VMIN SRAM with a disturb-free 8 T cell. The SRAM utilizes single-ended buffer Read, and cross-point data-aware Write Word-Line structure with adaptive VVSS control to eliminate Read disturb and Half-Select disturb, thus facilitating bit-interleaving architecture and achieving low VMIN. A 512 Kb test chip is implemented in UMC 55 nm Standard Performance (SP) CMOS technology. The measurement results demonstrate operating frequency of 943 MHz at 1.2 V VDD and 209 MHz at 0.6 V VDD.
Year
DOI
Venue
2011
10.1109/SOCC.2011.6085080
symposium on cloud computing
Keywords
Field
DocType
CMOS memory circuits,random-access storage,adaptive VVSS control,bit-interleaving architecture,cross-point data-aware write word-line structure,disturb-free 8T SRAM,disturb-free 8T cell,half-select disturb,high-performance low VMIN SRAM,single-ended buffer read,size 55 nm,standard performance CMOS technology,storage capacity 512 Kbit
Operating frequency,Computer science,Electronic engineering,Chip,CMOS,Real-time computing,Static random-access memory
Conference
ISSN
ISBN
Citations 
2164-1676 E-ISBN : 978-1-4577-1615-7
978-1-4577-1615-7
1
PageRank 
References 
Authors
0.38
2
19
Name
Order
Citations
PageRank
Hao-i Yang1416.20
Shih-Chi Yang210.38
Mao-Chih Hsia341.18
Yung-Wei Lin481.29
Yi-Wei Lin5123.66
Chien-Hen Chen691.65
Chi-Shin Chang792.22
Geng-Cing Lin892.54
Yin-Nien Chen9235.91
Ching-Te Chuang1046576.52
Wei Hwang1125444.40
Shyh-Jye Jou12420275.67
Nan-Chun Lien13134.18
Hung-yu Li14194.56
Kuen-Di Lee15486.10
Wei-Chiang Shih16394.41
Ya-Ping Wu17142.14
Wen-Ta Lee18165.45
Chih-Chiang Hsu19965.59