| A 40 nm 512 kb Cross-Point 8 T Pipeline SRAM With Binary Word-Line Boosting Control, Ripple Bit-Line and Adaptive Data-Aware Write-Assist | 5 | 0.49 | 2014 |
| A 40nm 1.0Mb 6T pipeline SRAM with digital-based Bit-Line Under-Drive, Three-Step-Up Word-Line, Adaptive Data-Aware Write-Assist with VCS tracking and Adaptive Voltage Detector for boosting control | 1 | 0.39 | 2013 |
| A 40nm 1.0Mb pipeline 6T SRAM with variation-tolerant Step-Up Word-Line and Adaptive Data-Aware Write-Assist | 1 | 0.37 | 2013 |
| High-Performance 0.6v V-Min 55nm 1.0mb 6t Sram With Adaptive Bl Bleeder | 1 | 0.39 | 2012 |
| A 55nm 0.5V 128Kb cross-point 8T SRAM with data-aware dynamic supply Write-assist | 2 | 0.41 | 2012 |
| An all-digital Read Stability and Write Margin characterization scheme for CMOS 6T SRAM array | 0 | 0.34 | 2012 |
| A 0.33-V, 500-kHz, 3.94- 40-nm 72-Kb 9T Subthreshold SRAM With Ripple Bit-Line Structure and Negative Bit-Line Write-Assist | 6 | 0.51 | 2012 |
| A 55nm 0.55v 6T SRAM with variation-tolerant dual-tracking word-line under-drive and data-aware write-assist | 5 | 0.69 | 2012 |
| Embedded SRAM ring oscillator for in-situ measurement of NBTI and PBTI degradation in CMOS 6T SRAM array | 0 | 0.34 | 2012 |
| A high-performance low VMIN 55nm 512Kb disturb-free 8T SRAM with adaptive VVSS control. | 1 | 0.38 | 2011 |
| Impacts of NBTI/PBTI on Timing Control Circuits and Degradation Tolerant Design in Nanoscale CMOS SRAM. | 14 | 0.71 | 2011 |
| Impacts of gate-oxide breakdown on power-gated SRAM | 0 | 0.34 | 2011 |
| Impacts of NBTI and PBTI on power-gated SRAM with high-k metal-gate devices | 4 | 0.47 | 2009 |
| Low-power floating bitline 8-T SRAM design with write assistant circuits | 1 | 0.38 | 2008 |
