Name
Abstract | ||
|---|---|---|
We propose REWIRED (REgister Write Inhibition by REsource Dedication), a technique for reducing power during high level synthesis (HLS) by selectively inhibiting the storage of function unit (FU) output data into registers. Registers are generally inferred in HLS when data produced in one clock cycle is used in a later cycle. However, when it can be established that the input registers to an FU are not changing values during a certain period, the outputs during this period can be directly read off the FU output pins without needing to store them in registers. When the life-times of such data are short, it may be possible to completely eliminate the register storage operation, thereby reducing power. We present a genetic algorithm formulation and a heuristic for maximizing the number of register stores that can be inhibited in a scheduled data flow graph (DFG) during behavioral synthesis.
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Year | DOI | Venue |
|---|---|---|
2008 | 10.1109/ASPDAC.2008.4483960 | ASP-DAC |
Keywords | Field | DocType |
register storage operation,fu output pin,output data,register write inhibition,later cycle,certain period,scheduled data flow graph,input register,behavioral synthesis,resource dedication,high level synthesis,clock cycle,functional unit,data flow graph,registers,genetic algorithm,heuristic algorithm,writing,power dissipation,genetic algorithms,shift registers | Shift register,Heuristic,Heuristic (computer science),Computer science,High-level synthesis,Data-flow analysis,Electronic engineering,Cycles per instruction,Genetic algorithm,Behavioral synthesis | Conference |
ISSN | ISBN | Citations |
2153-6961 | 978-1-4244-1922-7 | 1 |
PageRank | References | Authors |
0.35 | 12 | 4 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Pushkar Tripathi | 1 | 159 | 8.55 |
| Rohan Jain | 2 | 1 | 0.35 |
| Srikanth Kurra | 3 | 11 | 1.01 |
| Preeti Ranjan Panda | 4 | 786 | 89.40 |