Name
Abstract | ||
|---|---|---|
In this paper, we propose a memory efficient multi-rate Low Density Parity Check (LDPC) decoder for China Mobile Multimedia Broadcasting (CMMB). We find the best trade-off between the performance and the circuit area by designing a partially parallel decoder which is capable of passing multiple messages in parallel. By designing an efficient address generation unit (AGU) with an index matrix, we could reduce both the amount of memory requirement and the complexity of computation. The proposed regular LDPC decoder was designed in Verilog HDL and was synthesized by Synopsys¿ Design Compiler using Chartered 0.18 ¿m CMOS cell library. The synthesized design has the gate size of 455 K (in NAND2). For the two code rates supported by CMMB, the rate-1/2 decoder has a throughput of 14.32 Mbps, and the rate-3/4 decoder has a throughput of 26.97 Mbps. Compared with a conventional LDPC for CMMB, our proposed design requires only 0.39% of the memory. |
Year | DOI | Venue |
|---|---|---|
2009 | 10.1109/TCE.2009.5373744 | IEEE Trans. Consumer Electronics |
Keywords | Field | DocType |
china mobile multimedia broadcasting,cmos integrated circuits,synthesized design,mobile communication,proposed regular ldpc decoder,cmos cell library,cmmb,broadcasting,hardware description languages,multi-rate support,bit rate 14.32 mbit/s,index matrix,low density parity check decoder,memory requirement,parallel decoder,conventional ldpc,size 0.18 mum,memory efficient multi-rate,efficient address generation unit,address generation unit,design compiler,partially parallel decoder,low density parity check (ldpc) codes,parity check codes,multi-rate regular ldpc decoder,bit rate 26.97 mbit/s,multimedia communication,verilog hdl,decoding,proposed design,partially parallel decoder.,throughput,circuits,memory management,low density parity check,ldpc code,indexation,indexes | Address generation unit,Low-density parity-check code,Computer science,Parallel computing,Electronic engineering,Memory management,Soft-decision decoder,Throughput,Verilog,Decoding methods,Hardware description language | Journal |
Volume | Issue | ISSN |
55 | 4 | 0098-3063 |
Citations | PageRank | References |
8 | 0.72 | 8 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| So-Jin Lee | 1 | 9 | 1.54 |
| Joo-Yul Park | 2 | 76 | 4.90 |
| Ki-seok Chung | 3 | 189 | 18.76 |