Name
Abstract | ||
|---|---|---|
The need for hardware acceleration of Network-on-Chip (NoC) simulation has been motivated by their growing complexity and large design space. NoC simulation can exploit the inherent concurrency in hardware by using FPGA based emulators. For trace-driven NoC emulators, we enhance this raw hardware speedup by exploiting the traffic characteristics for a more efficient utilization of hardware. We propose a technique, OTO-NoC-Sim, to reduce NoC emulation time by scheduling network transactions in an out-of-time order. Our simulation technique addresses the challenges arising out of an out-of-time-order scheduling in maintaining the correctness of statistics measured. Our experiments indicate that our proposed technique reduces the average emulation time by 3× for multi-threaded applications and by 3.5× for multi-programmed benchmarks when compared to a conventional FPGA emulation. |
Year | DOI | Venue |
|---|---|---|
2011 | 10.1145/2039370.2039418 | Hardware/Software Codesign and System Synthesis |
Keywords | Field | DocType |
noc simulation,trace-driven noc emulators,noc emulation time,temporal decoupling,simulation technique,out-of-time-order scheduling,proposed technique,trace-driven noc emulation,hardware acceleration,average emulation time,raw hardware speedup,conventional fpga emulation,hardware accelerator,network on chip,multi threading,field programmable gate arrays | Multithreading,Computer science,Scheduling (computing),Real-time computing,Speedup,Hardware emulation,Computer architecture,Parallel computing,Field-programmable gate array,Network on a chip,Emulation,Hardware acceleration,Embedded system | Conference |
ISBN | Citations | PageRank |
978-1-4503-0715-4 | 1 | 0.40 |
References | Authors | |
15 | 4 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Gummidipudi Krishnaiah | 1 | 14 | 2.14 |
| B.V.N. Silpa | 2 | 17 | 2.39 |
| Preeti Ranjan Panda | 3 | 786 | 89.40 |
| Anshul Kumar | 4 | 399 | 48.45 |