Paper Info
Title
A 2/5 Mw Cmos Delta Sigma Modulator Employed In An Improved Gsm/Umts Receiver Structure
Abstract
In this paper, the design of a reconfigurable low-power low-pass Switched Capacitor Delta-Sigma (SC Delta Sigma) modulator for GSM/UMTS standards used in an optimum low-IF(LIF)/Zero-IF(ZIF) receiver architecture is described. A new approach for obtaining the optimum modulator coefficients is developed which results in relaxed specifications of the circuit components, aggressive noise transfer function (NTF) and a signal transfer function (STF) with the blocker-rejection property. The modulator employs a second/third-order single-stage dual-quantizer structure. It achieves 85.6 dB/57 dB SNDR and -0.2 dBFS/-0.05 dBFS overload factor at 0.2/2MHz bandwidth for GSM/UMTS standards and consumes only 2 mW/5 mW from a single 1.8 V supply in a 0.18 mu m 1P6M CMOS process. The maximum spread of the modulator capacitors is 105.
Year
DOI
Venue
2005
10.1587/elex.2.267
IEICE ELECTRONICS EXPRESS
Keywords
DocType
Volume
delta-sigma modulator, capacitor spread, dual-quantizer
Journal
2
Issue
ISSN
Citations 
8
1349-2543
0
PageRank 
References 
Authors
0.34
0
4
Name
Order
Citations
PageRank
Ali Zahabi123.26
Omid Shoaei213440.66
Y. Koolivand322.58
Parviz Jabedar-maralani4345.78