Name
Abstract | ||
|---|---|---|
We present self-calibration techniques for an interleaved SAR (Successive Approximation Register) ADC. The calibration technique is based on hardware corrections for linearity of single stage, gain error and mismatch errors of parallel ADCs. The 4-interleaved 11-bit ADC has been fabricated in a 0.18-mu m CMOS process. Using the calibrations, measurement and calculation results show that the differences of ramp characteristic among the 4-interleaving ADC can be decresased to under 0.63 LSB. |
Year | DOI | Venue |
|---|---|---|
2010 | 10.1587/transele.E93.C.1630 | IEICE TRANSACTIONS ON ELECTRONICS |
Keywords | Field | DocType |
analog to digital converter, charge redistribution type digital to analog converter, successive approximation architecture, calibration technique | Flight dynamics (spacecraft),Capacitor,Linearity,Electronic engineering,Analog-to-digital converter,Engineering,Successive approximation ADC,Integrating ADC,Calibration,Least significant bit | Journal |
Volume | Issue | ISSN |
E93C | 11 | 1745-1353 |
Citations | PageRank | References |
2 | 0.44 | 0 |
Authors | ||
4 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Yasuhide Kuramochi | 1 | 3 | 0.82 |
| Masayuki Kawabata | 2 | 17 | 4.61 |
| Koichiro Uekusa | 3 | 11 | 2.35 |
| Akira Matsuzawa | 4 | 465 | 88.10 |