Paper Info
Title
Sequential optimization in the absence of global reset
Abstract
We study the problem of optimizing synchronous sequential circuits. There have been previous efforts to optimize such circuits. However, all previous attempts make implicit or explicit assumptions about the design or the environment of the design. For example, it is widespread practice to assume the existence of a hardware reset line and consequently a fixed power-up state; in the absence of the same, a common premise is that the design's environment will apply an initializing sequence. We review the concept of safe replaceability which does away with these assumptions and the delay-safe replaceability notion, which is applicable when the design's output is not used for a certain number of cycles after power-up. We then develop procedures for optimizing the combinational next-state and output logic, as well as routines for reencoding the state space and removing state bits under these replaceability criteria. Experimental results demonstrate the effectiveness of our algorithms.
Year
DOI
Venue
2003
10.1145/762488.762493
ACM Trans. Design Autom. Electr. Syst.
Keywords
Field
DocType
additional key words and phrases: sequential logic synthesis,state bit,global reset,sequential optimization,previous attempt,fixed power-up state,previous effort,safe replaceability,delay-safe replaceability notion,certain number,no-reset latches,sequential logic synthesis,state space,output logic,replaceability criterion,logic synthesis,sequential circuits
Sequential optimization,Hardware reset,Sequential logic,Sequential logic synthesis,Computer science,Parallel computing,Real-time computing,Premise,Initialization,Electronic circuit,State space
Journal
Volume
Issue
ISSN
8
2
1084-4309
Citations 
PageRank 
References 
1
0.37
27
Authors
5
Name
Order
Citations
PageRank
Vigyan Singhal196186.42
Carl Pixley241844.09
Adnan Aziz31778149.76
Shaz Qadeer43257239.11
Robert K. Brayton56224883.32