Name
Abstract | ||
|---|---|---|
IDDQ testing has become a widely accepted defect detection technique in CMOS ICs. However, its effectiveness in very deep submicron technologies is threatened by the increased transistor leakage current. In this paper, we propose a technique for the elimination, during testing, of the normal leakage current from the sensing node of a circuit under test. In this way the already known in the open literature IDDQ sensing techniques can be applied in the nanometer technologies. |
Year | DOI | Venue |
|---|---|---|
2002 | 10.1016/S0167-9260(02)00023-8 | Integration |
Keywords | Field | DocType |
IDDQ testing,Current monitoring,Design for testability | Design for testing,Leakage (electronics),Computer science,CMOS,Electronic engineering,Iddq testing,Nanometre,Transistor,Electrical engineering,Circuit under test | Journal |
Volume | Issue | ISSN |
31 | 2 | 0167-9260 |
Citations | PageRank | References |
0 | 0.34 | 11 |
Authors | ||
5 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Y. Tsiatouhas | 1 | 68 | 11.07 |
| Y. Moisiadis | 2 | 1 | 6.27 |
| Th. Haniotakis | 3 | 43 | 7.74 |
| D. Nikolos | 4 | 291 | 31.38 |
| A. Arapoyanni | 5 | 39 | 11.46 |