Name
Abstract | ||
|---|---|---|
We are concerned with optimizing gate-level netlists containing "e;black boxes,"e; that is, components whose functionality is not available to the optimization tool. We establish a notion of equivalence for gate-level netlists containing black boxes, and prove that it is sound and complete. We show that conventional approaches to optimizing such netlists fail to fully exploit the don't care flexibility available for synthesis. Based on our new notion of equivalence, we introduce a procedure that computes the complete don't care set. Experiments indicate that our procedure can achieve more minimization than conventional synthesis. |
Year | DOI | Venue |
|---|---|---|
2001 | 10.1145/502175.502184 | ACM Trans. Design Autom. Electr. Syst. |
Keywords | Field | DocType |
optimizing design,gate-level netlists,conventional synthesis,optimization tool,conventional approach,don't cares,black box,hierarchical logic synthesis,new notion,ip-based design,optimal design,logic synthesis | Computer science,Theoretical computer science,Exploit,Equivalence (measure theory),Minification,Black box | Journal |
Volume | Issue | ISSN |
6 | 4 | 1084-4309 |
Citations | PageRank | References |
0 | 0.34 | 11 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Tai-Hung Liu | 1 | 17 | 1.90 |
| Adnan Aziz | 2 | 1778 | 149.76 |
| Vigyan Singhal | 3 | 961 | 86.42 |