Name
Title | ||
|---|---|---|
Design Methodology For Determining The Number Of Stages In A Cascaded Time Amplifier To Minimize Area Consumption |
Abstract | ||
|---|---|---|
This paper describes a design methodology for determining the number of stages in a cascaded time amplifier to minimize the area consumption. The total area consumption is categorized into three parts, which allows mathematical analysis and optimization to be performed. A combination of the proposed mathematical analysis and 2D mapping can determine the number of stages to minimize the area consumption. |
Year | DOI | Venue |
|---|---|---|
2013 | 10.1587/elex.10.20130289 | IEICE ELECTRONICS EXPRESS |
Keywords | Field | DocType |
time amplifier, CMOS, integrated circuits, design methodology, design for testability | Design for testing,Computer science,Design methods,CMOS,Electronic engineering,Integrated circuit,Amplifier | Journal |
Volume | Issue | ISSN |
10 | 11 | 1349-2543 |
Citations | PageRank | References |
1 | 0.37 | 0 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Kiichi Niitsu | 1 | 126 | 38.14 |
| Naohiro Harigai | 2 | 6 | 2.58 |
| Haruo Kobayashi | 3 | 1 | 0.37 |