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NAOHIRO HARIGAI
Author Info
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Name
Affiliation
Papers
NAOHIRO HARIGAI
Gunma Univ, Fac Sci & Technol, Div Elect & Informat, Kiryu, Gunma 3768515, Japan
7
Collaborators
Citations
PageRank
13
6
2.58
Referers
Referees
References
19
81
36
Publications (7 rows)
Collaborators (13 rows)
Referers (19 rows)
Referees (81 rows)
Title
Citations
PageRank
Year
A CMOS PWM Transceiver Using Self-Referenced Edge Detection
0
0.34
2015
A Low-Offset Cascaded Time Amplifier With Reconfigurable Inter-Stage Connection
0
0.34
2014
Design Methodology For Determining The Number Of Stages In A Cascaded Time Amplifier To Minimize Area Consumption
1
0.37
2013
A Feed-Forward Time Amplifier Using A Phase Detector And Variable Delay Lines
1
0.37
2013
A clock jitter reduction circuit using gated phase blending between self-delayed clock edges
2
0.41
2012
An on-chip timing jitter measurement circuit using a self-referenced clock and a cascaded time difference amplifier with duty-cycle compensation
2
0.41
2011
Analysis of jitter accumulation in interleaved phase frequency detectors for high-accuracy on-chip jitter measurements
0
0.34
2011
1