Name
Abstract | ||
|---|---|---|
In multiprocessors, performance improvement is typically achieved by exploring parallelism with fixed granularities, such as instruction-level, task-level, or data-level parallelism. We introduce a new reconfiguration mechanism that facilitates variations in these granularities in order to optimize resource utilization in addition to performance improvements. Our reconfigurable multiprocessor QuadroCore combines the advantages of reconfigurability and parallel processing. In this article, a unified hardware-software approach for the design of our QuadroCore is presented. This design flow is enabled via compiler-driven reconfiguration which matches application-specific characteristics to a fixed set of architectural variations. A special reconfiguration mechanism has been developed that alters the architecture within a single clock cycle. The QuadroCore has been implemented on Xilinx XC2V6000 for functional validation and on UMC’s 90nm standard cell technology for performance estimation. A diverse set of applications have been mapped onto the reconfigurable multiprocessor to meet orthogonal performance characteristics in terms of time and power. Speedup measurements show a 2--11 times performance increase in comparison to a single processor. Additionally, the reconfiguration scheme has been applied to save power in data-parallel applications. Gate-level simulations have been performed to measure the power-performance trade-offs for two computationally complex applications. The power reports confirm that introducing this scheme of reconfiguration results in power savings in the range of 15--24%. |
Year | DOI | Venue |
|---|---|---|
2010 | 10.1145/1839480.1839487 | ACM Transactions on Reconfigurable Technology and Systems (TRETS) |
Keywords | Field | DocType |
performance improvement,reconfigurable multiprocessor,compiler-driven reconfiguration,new reconfiguration mechanism,orthogonal performance characteristic,performance estimation,reconfiguration result,reconfiguration scheme,special reconfiguration mechanism,times performance increase,Compile-Time Analysis,Runtime Reconfiguration | Reconfigurability,Computer science,Compile time,Parallel computing,Design flow,Real-time computing,Multiprocessing,Cycles per instruction,Control reconfiguration,Embedded system,Performance improvement,Speedup | Journal |
Volume | Issue | ISSN |
3 | 3 | 1936-7406 |
Citations | PageRank | References |
0 | 0.34 | 11 |
Authors | ||
6 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Madhura Purnaprajna | 1 | 47 | 6.34 |
| Mario Porrmann | 2 | 420 | 50.91 |
| Ulrich Rueckert | 3 | 16 | 2.51 |
| Michael Hußmann | 4 | 1 | 1.13 |
| Michael Thies | 5 | 84 | 10.01 |
| Uwe Kastens | 6 | 406 | 55.65 |