Name
Abstract | ||
|---|---|---|
Controllabilities and detectabilities for a line in a digital circuit are defined as absolute probabilities while observabilities are defined as conditional probabilities. For exact computation of these probabilities, a divide-and-conquer technique is developed in terms of subcircuits covering the original circuit. The subcircuits, called supergates, completely enclose all reconvergent fanouts. Computation of probabilities requires conditional computations within supergates with specific logical value assignments to reconvergent fanout inputs. Combining the conditional values weighted with corresponding assignment probabilities gives the total probability. Detectability computation is direct and does not require the generation of an exclusive-or function or the insertion of auxiliary gates as needed in other methods that convert the detectability problem into a controllability problem. Techniques are suggested for limiting computational effert in circuits with very large supergates where approximate computation may be desirable. |
Year | DOI | Venue |
|---|---|---|
1989 | 10.1016/0167-9260(89)90059-X | Integration |
Keywords | DocType | Volume |
random-pattern testability,probabilistic testability,new model,detection probability,cad,testability measures,supergates,combinational circuit | Journal | 7 |
Issue | ISSN | Citations |
1 | Integration, the VLSI Journal | 26 |
PageRank | References | Authors |
4.25 | 11 | 2 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Sharad C. Seth | 1 | 671 | 93.61 |
| Vishwani D. Agrawal | 2 | 3502 | 470.06 |