Name
Abstract | ||
|---|---|---|
We study the problem of mapping concurrent tasks of an application to cores of a chip multiprocessor that utilize circuit-switched interconnect and global asynchronous local synchronous (GALS) clocking domains. We develop a configurable algorithm that naturally handles a number of practical requirements, such as architectural features of the target platform, core failures, and hardware accelerators, and in addition, is scalable to a large number of tasks and cores. Experiments with several real life applications show that our algorithm outperforms manual mapping, integer linear programming-based mapping after ten days of solver run time, and a recent packet-switched network on chip-based task mapper through which, we underscore the unique requirements of task mapping for circuit-switched GALS architectures. |
Year | DOI | Venue |
|---|---|---|
2014 | 10.1109/TCAD.2014.2299958 | Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions |
Keywords | DocType | Volume |
integer programming,integrated circuit interconnections,linear programming,multiprocessing systems,network-on-chip,packet switching,switching networks,circuit-switched GALS chip multiprocessor platforms,circuit-switched interconnect,concurrent task mapping,configurable algorithm,core failures,global asynchronous local synchronous clocking domains,hardware accelerators,integer linear programming-based mapping,packet-switched network on chip-based task mapper,target platform,time-scalable mapping,Algorithm,chip multiprocessor (CMP),global asynchronous local synchronous (GALS),task to processor mapping | Journal | 33 |
Issue | ISSN | Citations |
5 | 0278-0070 | 0 |
PageRank | References | Authors |
0.34 | 0 | 5 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Mohammad H. Foroozannejad | 1 | 11 | 2.33 |
| Matin Hashemi | 2 | 63 | 8.48 |
| Alireza Mahini | 3 | 4 | 1.83 |
| Bevan M. Baas | 4 | 295 | 27.78 |
| Soheil Ghiasi | 5 | 352 | 34.74 |