Name
Title | ||
|---|---|---|
A 0.4-to-3GHz digital PLL with supply-noise cancellation using deterministic background calibration. |
Year | DOI | Venue |
|---|---|---|
2011 | 10.1109/ISSCC.2011.5746233 | ISSCC |
Keywords | Field | DocType |
oscillator phase noise,digital filters,process variation,jitter,noise,ring oscillator,phase locked loops,low dropout regulator,calibration,oscillators | Phase-locked loop,Ring oscillator,Digital filter,Computer science,Oscillator phase noise,Electronic engineering,DPLL algorithm,Jitter,Active noise control,Electrical engineering,Low-dropout regulator | Conference |
Citations | PageRank | References |
11 | 1.16 | 2 |
Authors | ||
5 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Amr Elshazly | 1 | 242 | 28.08 |
| Rajesh Inti | 2 | 118 | 13.20 |
| Wenjing Yin | 3 | 65 | 8.81 |
| Brian Young | 4 | 118 | 12.20 |
| Pavan Kumar Hanumolu | 5 | 554 | 84.82 |