Name
Abstract | ||
|---|---|---|
Dynamic binary translation (DBT) is a core technologyto many important applications such as system virtualization, dynamic binary instrumentation, and security. However, there are several factors that often impede its performance: 1) emulation overhead before translation; 2) translation and optimization overhead; and 3) translated code quality. The issues also include its retargetabilitythat supports guest applications from different instruction-set architectures (ISAs) to host machines also with different ISAs-an important feature to system virtualization. In this work, we take advantage of the ubiquitous multicore platforms, and use a multithreaded approach to implement DBT. By running the translator and the dynamic binary optimizer on different cores with different threads, it could off-load the overhead incurred by DBT on the target applications; thus, afford DBT of more sophisticated optimization techniques as well as its retargetability. Using QEMU (a popular retargetable DBT for system virtualization) and Low-Level Virtual Machine (LLVM) as our building blocks, we demonstrated in a multithreaded DBT prototype, called Hybrid-QEMU (HQEMU), that it could improve QEMU performance by a factor of 2.6x and 4.1x on the SPEC CPU2006 integer and floating point benchmarks, respectively, for dynamic translation of x86 code to run on x86-64 platforms. For ARM codes to x86-64 platforms, HQEMU can gain a factor of 2.5x speedup over QEMU for the SPEC CPU2006 integer benchmarks. We also address the performance scalability issue of multithreaded applications across ISAs. We identify two major impediments to performance scalability in QEMU: 1) coarse-grained locks used to protect shared data structures, and 2) inefficient emulation of atomic instructions across ISAs. We proposed two techniques to mitigate those problems: 1) using indirect branch translation caching (IBTC) to avoid frequent accesses to locks, and 2) using lightweight memory transactions to emulate atomic instru- tions across ISAs. Our experimental results show that for multithread applications, HQEMU achieves 25X speedups over QEMU for the PARSEC benchmarks. |
Year | DOI | Venue |
|---|---|---|
2014 | 10.1109/TPDS.2013.56 | IEEE Trans. Parallel Distrib. Syst. |
Keywords | DocType | Volume |
optimisation,different core,multithreaded approach,translation overhead,dynamic translation,popular retargetable dbt,feedback-directed optimization,multithreaded dbt prototype,translated code quality,retargetable dynamic binary translation,system virtualization,multi-threading,hardware performance monitoring,dynamic binary optimizer,traces,ubiquitous multicore platforms,atomic instruction,qemu,multiprocessing systems,coarse-grained locks,lightweight memory transactions,dynamic binary translation,instruction-set architectures,llvm,low-level virtual machine,qemu performance,optimization overhead,indirect branch translation caching,ibtc,multicores,different isas,shared data structures,emulation overhead,multicore processing,scalability,emulation,instruction sets,merging,benchmark testing,optimization,multi threading | Journal | 25 |
Issue | ISSN | Citations |
3 | 1045-9219 | 3 |
PageRank | References | Authors |
0.41 | 12 | 8 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Ding-Yong Hong | 1 | 85 | 9.88 |
| Jan-Jan Wu | 2 | 550 | 59.21 |
| Pen-Chung Yew | 3 | 1430 | 133.52 |
| Wei-Chung Hsu | 4 | 719 | 58.87 |
| Chun-Chen Hsu | 5 | 127 | 10.86 |
| Pangfeng Liu | 6 | 661 | 69.35 |
| Chien-Min Wang | 7 | 218 | 28.55 |
| Yeh-Ching Chung | 8 | 983 | 97.16 |