Paper Info
Title
HACS: A novel cost aware paradigm promising fault tolerance on mesh-based network on chip architecture
Abstract
As the integration of transistors on today's embedded systems scales, so does the shrinking size of chips, thus making the on-chip communication a challenging issue on the VLSI designs. However, network on chips have emerged as a promising technology to tackle the on-chip communication constraints. Likewise, the reliability issues have become the salient problem, since regarding to the inaccessible failures of on-chip elements, there must be some levels of embedded fault tolerance techniques. In this paper, an innovated technique is revealed providing fault tolerance in the on-chip networks over single and multiple permanent switch failures. The experimental results achieved by the system simulation in SystemC TLM environment are validated with the mathematical analysis modeled for system reliability that we extend in this paper, which demonstrate the extensive reliability enhancement of this paradigm. Along with the system improvement, silicon area overhead is calculated utilizing VHDL low level simulation and Orion synthesis.
Year
DOI
Venue
2012
10.1016/j.compeleceng.2012.02.004
Computers & Electrical Engineering
Keywords
Field
DocType
vhdl low level simulation,mesh-based network,system simulation,on-chip communication constraint,system reliability,system improvement,chip architecture,on-chip element,reliability issue,extensive reliability enhancement,on-chip network,aware paradigm promising fault,on-chip communication,novel cost
Network on,Computer science,Computer network,SystemC,Real-time computing,Fault tolerance,Network on chip architecture,VHDL,Transistor,Very-large-scale integration,Embedded system,Salient
Journal
Volume
Issue
ISSN
38
4
0045-7906
Citations 
PageRank 
References 
0
0.34
11
Authors
4
Name
Order
Citations
PageRank
Melika Tinati100.34
Ahmad Khademzadeh230832.82
Ali Afzali-kusha336554.65
Majid Janidarmian4848.81