| Distributing DNN training over IoT edge devices based on transfer learning | 0 | 0.34 | 2022 |
| An Adaptive Memory-Side Encryption Method for Improving Security and Lifetime of PCM-Based Main Memory | 0 | 0.34 | 2022 |
| Optimum distribution of seismic energy dissipation devices using neural network and fuzzy inference system | 0 | 0.34 | 2021 |
| Res-DNN: A Residue Number System-Based DNN Accelerator Unit | 5 | 0.45 | 2020 |
| Block-Based Carry Speculative Approximate Adder for Energy-Efficient Applications | 2 | 0.37 | 2020 |
| Low-Power Data Encoding/Decoding for Energy-Efficient Static Random Access Memory Design | 0 | 0.34 | 2019 |
| An Energy-Efficient, Yet Highly-Accurate, Approximate Non-Iterative Divider | 1 | 0.37 | 2018 |
| TheSPoT: Thermal Stress-Aware Power and Temperature Management for Multiprocessor Systems-on-Chip. | 10 | 0.59 | 2018 |
| Toward Approximate Computing for Coarse-Grained Reconfigurable Architectures. | 1 | 0.48 | 2018 |
| LETAM: A low energy truncation-based approximate multiplier. | 2 | 0.39 | 2017 |
| An energy and area efficient yet high-speed square-root carry select adder structure. | 2 | 0.40 | 2017 |
| All-Region Statistical Model for Delay Variation Based on Log-Skew-Normal Distribution. | 4 | 0.45 | 2016 |
| High-Speed and Energy-Efficient Carry Skip Adder Operating Under a Wide Range of Supply Voltage Levels | 3 | 0.42 | 2016 |
| Seerad: A High Speed Yet Energy-Efficient Rounding-Based Approximate Divider | 4 | 0.48 | 2016 |
| Hybrid TFET-MOSFET circuits: An approach to design reliable ultra-low power circuits in the presence of process variation | 1 | 0.35 | 2016 |
| Yield and Speedup Improvements in Extensible Processors by Allocating Extra Cycles to Some Custom Instructions. | 0 | 0.34 | 2016 |
| Power and energy reduction of racetrack-based caches by exploiting shared shift operations | 0 | 0.34 | 2016 |
| Read static noise margin aging model considering SBD and BTI effects for FinFET SRAMs. | 0 | 0.34 | 2016 |
| A thermal stress-aware algorithm for power and temperature management of MPSoCs | 1 | 0.37 | 2015 |
| Dynamic Flip-Flop Conversion: A Time-Borrowing Method for Performance Improvement of Low-Power Digital Circuits Prone to Variations | 7 | 0.50 | 2015 |
| Workload and temperature dependent evaluation of BTI-induced lifetime degradation in digital circuits | 2 | 0.37 | 2015 |
| High-performance and high-yield 5 nm underlapped FinFET SRAM design using P-type access transistors | 0 | 0.34 | 2015 |
| Design of NBTI-resilient extensible processors | 1 | 0.35 | 2015 |
| OPLE: A Heuristic Custom Instruction Selection Algorithm Based on Partitioning and Local Exploration of Application Dataflow Graphs | 1 | 0.36 | 2015 |
| CSAM: A clock skew-aware aging mitigation technique. | 2 | 0.38 | 2015 |
| A near-threshold 7T SRAM cell with high write and read margins and low write time for sub-20 nm FinFET technologies. | 0 | 0.34 | 2015 |
| A heuristic machine learning-based algorithm for power and thermal management of heterogeneous MPSoCs | 3 | 0.42 | 2015 |
| Simultaneous power control and power management algorithm with sector-shaped topology for wireless sensor networks | 1 | 0.36 | 2015 |
| A Finfet Sram Cell Design With Bti Robustness At High Supply Voltages And High Yield At Low Supply Voltages | 2 | 0.36 | 2015 |
| Improving efficiency of extensible processors by using approximate custom instructions | 6 | 0.49 | 2014 |
| Implementation-aware selection of the custom instruction set for extensible processors. | 1 | 0.37 | 2014 |
| Data Encoding Techniques for Reducing Energy Consumption in Network-on-Chip | 13 | 0.57 | 2014 |
| Robust FinFET SRAM design based on dynamic back-gate voltage adjustment. | 9 | 0.81 | 2014 |
| Impact of Process Variations on Speedup and Maximum Achievable Frequency of Extensible Processors | 2 | 0.39 | 2014 |
| Dynamic Flip-Flop conversion to tolerate process variation in low power circuits | 3 | 0.43 | 2014 |
| Capturing and mitigating the NBTI effect during the design flow for extensible processors | 1 | 0.34 | 2013 |
| Robust polysilicon gate FinFET SRAM design using dynamic back-gate bias | 1 | 0.39 | 2013 |
| Considering the effect of process variations during the ISA extension design flow | 2 | 0.36 | 2013 |
| Self-Impact Of Nbti Effect On The Degradation Rate Of Threshold Voltage In Pmos Transistors | 1 | 0.37 | 2013 |
| Modeling symmetrical independent gate FinFET using predictive technology model | 2 | 0.40 | 2013 |
| An analytical model for read static noise margin including soft oxide breakdown, negative and positive bias temperature instabilities. | 2 | 0.45 | 2013 |
| A new merit function for custom instruction selection under an area budget constraint | 1 | 0.40 | 2013 |
| Statistical estimation of leakage power dissipation in nano-scale complementary metal oxide semiconductor digital circuits using generalised extreme value distribution. | 2 | 0.43 | 2012 |
| Adaptive Input-Output Selection Based On-Chip Router Architecture | 0 | 0.34 | 2012 |
| MEA: an energy efficient algorithm for dense sector-based wireless sensor networks. | 16 | 0.49 | 2012 |
| High-performance low-leakage regions of nano-scaled CMOS digital gates under variations of threshold voltage and mobility | 3 | 0.48 | 2012 |
| An architecture-level approach for mitigating the impact of process variations on extensible processors | 10 | 0.57 | 2012 |
| HACS: A novel cost aware paradigm promising fault tolerance on mesh-based network on chip architecture | 0 | 0.34 | 2012 |
| An accurate analytical I-V model for sub-90-nm MOSFETs and its application to read static noise margin modeling | 0 | 0.34 | 2012 |
| Modeling read SNM considering both soft oxide breakdown and negative bias temperature instability. | 2 | 0.46 | 2012 |
