Name
Abstract | ||
|---|---|---|
This paper presents a VLSI implementation of a low-density parity check (LDPC) decoder that achieves 2.4 Gbps throughput yet permits real-time configuration of (1) rate, (2) code length, and (3) the parity equations. This decoder can be programmed in the field, much like an FPGA. We describe the architectural, circuit-level and layout-level details of our implementation. Our design can handle variable rate codes of length up to 1024, and is implemented in a 0.1 mum VLSI fabrication process. Our design has a die size of 12 mm by 8 mm and a power consumption of 7 W. This implementation can be extended to handle longer codes in a partially parallel manner, and allow for on-the-fly modification of the code |
Year | DOI | Venue |
|---|---|---|
2006 | 10.1109/ICASSP.2006.1660818 | ICASSP (3) |
Keywords | Field | DocType |
7 w,very large scale integration,regular ldpc codes,low-density parity check decoder,vlsi,variable rate codes,2.4 gbit/s,parity check codes,high-speed fully-programmable vlsi decoder,decoding,ldpc code,throughput,real time,process design,field programmable gate arrays,low density parity check,variable rate,circuits,fabrication | Parity bit,Computer science,Low-density parity-check code,Parallel computing,Field-programmable gate array,Soft-decision decoder,Throughput,Decoding methods,Very-large-scale integration,Power consumption | Conference |
Volume | ISSN | ISBN |
3 | 1520-6149 | 1-4244-0469-X |
Citations | PageRank | References |
2 | 0.44 | 8 |
Authors | ||
6 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Euncheol Kim | 1 | 23 | 5.84 |
| Nikhil Jayakumar | 2 | 215 | 20.42 |
| Pankaj Bhagawat | 3 | 16 | 2.20 |
| Anand Selvarathinam | 4 | 2 | 0.44 |
| Gwan Choi | 5 | 369 | 56.66 |
| Sunil P. Khatri | 6 | 1213 | 137.09 |