Name
Abstract | ||
|---|---|---|
Assembling a system on a chip using IP blocks is an error-prone, labor-intensive, and time-consuming process. Emerging high-level tools can help by automating many of the design tasks. |
Year | DOI | Venue |
|---|---|---|
2001 | 10.1109/54.953270 | IEEE Design & Test of Computers |
Keywords | Field | DocType |
high-level tool,time-consuming process,ip block,design task,system on a chip,high level synthesis,electronic design automation | Computer architecture,System on a chip,Computer science,High-level synthesis,Electronic design automation,Computer engineering,Embedded system | Journal |
Volume | Issue | ISSN |
18 | 5 | 0740-7475 |
Citations | PageRank | References |
35 | 4.09 | 2 |
Authors | ||
8 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Reinaldo A. Bergamaschi | 1 | 420 | 52.57 |
| Subhrajit Bhattacharya | 2 | 462 | 36.93 |
| Ronoldo Wagner | 3 | 35 | 4.09 |
| Colleen Fellenz | 4 | 35 | 4.09 |
| Michael Muhlada | 5 | 35 | 4.09 |
| William R. Lee | 6 | 35 | 4.09 |
| Foster White | 7 | 35 | 4.09 |
| Jean-Marc Daveau | 8 | 161 | 18.16 |