Name
Abstract | ||
|---|---|---|
This paper presents two iterative synthesis techniques between a high-level synthesizer (HLS) and the place and route tool to shorten the prolonged wire delay for a dynamically reconfigurable processor. At first, we use feedback wire delays for each context to a scheduler in the HLS. The experimental results showed that a critical-path delay was shorten 21% on average for applications with timing closure problems. Second, we skip the routing and estimate wire delays based on their congestions. The synthesis time was cut by 1/3 with only four points down on delay improvement rate. |
Year | DOI | Venue |
|---|---|---|
2010 | 10.1109/FPT.2010.5681481 | FPT |
Keywords | Field | DocType |
hls,high-level synthesizer,feedback wire delays,dynamically reconfigurable processor,iterative synthesis techniques,delays,wire congestion aware synthesis,critical-path delay,field programmable gate arrays,high level synthesis,iterative methods,critical path,place and route,convergence | Convergence (routing),Iterative method,Computer science,High-level synthesis,Field-programmable gate array,Place and route,Critical path delay,Real-time computing,Timing closure,Embedded system | Conference |
ISBN | Citations | PageRank |
978-1-4244-8980-0 | 0 | 0.34 |
References | Authors | |
6 | 5 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Takao Toi | 1 | 32 | 3.85 |
| Takumi Okamoto | 2 | 117 | 12.83 |
| Toru Awashima | 3 | 47 | 4.80 |
| Kazutoshi Wakabayashi | 4 | 219 | 23.60 |
| Hideharu Amano | 5 | 1375 | 210.21 |