Name
Abstract | ||
|---|---|---|
Computing cores to be implemented on FPGAs may involve divisions by small integer constants in fixed or floating point. This article presents a family of architectures addressing this need. They are derived from a simple recurrence whose body can be implemented very efficiently as a look-up table that matches the hardware resources of the target FPGA. For instance, division of a 32-bit integer by the constant 3 may be implemented by a combinatorial circuit of 48 LUT6 on a Virtex-5. Other options are studied, including iterative implementations, and architectures based on embedded memory blocks. This technique also computes the remainder. An efficient implementation of the correctly rounded division of a floating-point constant by such a small integer is also presented. |
Year | DOI | Venue |
|---|---|---|
2012 | 10.1007/978-3-642-28365-9_5 | ARC |
Keywords | Field | DocType |
hardware resource,table-based division,small integer constant,efficient implementation,32-bit integer,rounded division,combinatorial circuit,floating point,embedded memory block,small integer,computing core | Integer,Computer science,Floating point,Parallel computing,Remainder,Field-programmable gate array,Implementation,Trial division,Embedded memory | Conference |
Citations | PageRank | References |
6 | 0.63 | 7 |
Authors | ||
2 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Florent de Dinechin | 1 | 503 | 43.43 |
| Laurent-Stéphane Didier | 2 | 108 | 11.89 |