Two hardware implementations for modular multiplication in the AMNS: Sequential and semi-parallel | 0 | 0.34 | 2021 |
Hardware Optimization on FPGA for the Modular Multiplication in the AMNS Representation. | 0 | 0.34 | 2019 |
Hardware Division by Small Integer Constants. | 4 | 0.48 | 2017 |
Formatting Bits to Better Implement Signal Processing Algorithms. | 5 | 0.51 | 2014 |
Table-Based division by small integer constants | 6 | 0.63 | 2012 |
Sum-of-products evaluation schemes with fixed-point arithmetic, and their application to IIR filter implementation. | 7 | 0.69 | 2012 |
Range estimation of floating-point variables in Simulink models | 3 | 0.47 | 2012 |
A generalization of a fast RNS conversion for a new 4-modulus base | 10 | 1.22 | 2009 |
A Generalization of a Fast RNS Conversion for a New 4-Modulus Base | 0 | 0.34 | 2009 |
Une nouvelle base RNS à 4 moduli et son convertisseur vers le binaire | 0 | 0.34 | 2008 |
High Radix BKM Algorithm. | 0 | 0.34 | 2004 |
An RNS Montgomery Modular Multiplication Algorithm | 64 | 4.22 | 1998 |
An IWS Montgomery Modular Multiplication Algorithm | 6 | 1.56 | 1997 |
A New Euclidean Division Algorithm for Residue Number Systems | 3 | 0.41 | 1996 |