Name
Title | ||
|---|---|---|
Yield, Overall Test Environment Timing Accuracy, and Defect Level Trade-Offs for High-Speed Interconnect Device Testing |
Abstract | ||
|---|---|---|
This paper extends the model in [4] to be more realistic by including the effects of the test fixtures between a device under test and a tester. The paper enables analyzing the trade-offs that arise between the predicted yield and the required overall test environment timing accuracy (OTETA) which involves the tester overall timing accuracy (OTA) and the test fixtures' impacts. We specifically focus on the application of the extended model to predict the test yield of standard high-speed interconnects, such as PCI Express, RapidIO, and HyperTransport. The extended model reveals that achieving an actual yield of 80% with a defect level of 300 DPM (Defects Per Million) requires an equivalent OTETA that is about half the acceptable absolute limit of the tested parameter. |
Year | DOI | Venue |
|---|---|---|
2003 | 10.1109/ATS.2003.1250835 | ATS 2003: 12TH ASIAN TEST SYMPOSIUM, PROCEEDINGS |
Keywords | Field | DocType |
timing specifications testing,test environment,yield analysis,tester OTA and yield,high-speed interconnect testing | Test fixture,Device under test,Computer science,Automatic test equipment,Defects per million opportunities,Electronic engineering,RapidIO,PCI Express,Test compression,Reliability engineering,HyperTransport | Conference |
Citations | PageRank | References |
3 | 0.56 | 6 |
Authors | ||
4 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Baosheng Wang | 1 | 62 | 7.37 |
| Yong B. Cho | 2 | 4 | 1.59 |
| Sassan Tabatabaei | 3 | 162 | 21.81 |
| André Ivanov | 4 | 193 | 16.71 |