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ANDRÉ IVANOV
Author Info
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Name
Affiliation
Papers
ANDRÉ IVANOV
University of British Columbia, Vancouver, Canada
13
Collaborators
Citations
PageRank
21
193
16.71
Referers
Referees
References
428
218
108
Search Limit
100
428
Publications (13 rows)
Collaborators (21 rows)
Referers (100 rows)
Referees (100 rows)
Title
Citations
PageRank
Year
CORGIDS: A Correlation-based Generic Intrusion Detection System.
1
0.34
2018
A realistic timing test model and its applications in high-speed interconnect devices
0
0.34
2005
Crosstalk bounded uncorrelated jitter (BUJ) for high-speed interconnects
7
0.59
2005
An Analog Circuit Fault Characterization Methodology
1
0.36
2005
Timing analysis of network on chip architectures for MP-SoC platforms
33
2.42
2005
A retention-aware test power model for embedded SRAM
2
0.38
2005
Jitter Models for the Design and Test of Gbps-Speed Serial Interconnects
26
2.39
2004
A Scalable Communication-Centric SoC Interconnect Architecture
25
2.09
2004
Structured interconnect architecture: a solution for the non-scalability of bus-based SoCs
18
1.62
2004
Yield, Overall Test Environment Timing Accuracy, and Defect Level Trade-Offs for High-Speed Interconnect Device Testing
3
0.56
2003
Design of a switch for network on chip applications
69
4.48
2003
CMOS Differential and Absolute Thermal Sensors
7
0.77
2001
Catastrophic Short and Open Fault Detection in Bipolar CML Circuits: A Case Study
1
0.36
2000
1